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Introduction to Pascal A1 ASIC architecture

created by Pascal Project |

The futures and concept of Pascal A1 ASIC architecture

Main architecture conception and basic features of ASIC device

  1. All parts of system are connected via common high capacity computer bus, this fact allows us to use shared memory RAM (64GB) and Processors’ resources.
  2. Data needed for mining certain mathematical algorithms (for example 10 for basic device, or 20 and more for advanced version)  is stored in Read-only memory (ROM). In Pascal A1 ASIC, ROM is used as an analogy of HDD in stationary PC. ROM helps us to solve problem of implementation of different hashing algorithms in one circuit from the software perspective.
  3. We plan to use at least two programmable logic devices (PDL) modules on the board. It allows ASIC to work simultaneously with two mining algorithms, for example Ethash and Equialhash, or Ethash and DASH with high capacity.
  4. One of PLDs has additional RAM memory (32GB) that is needed for complicated and specified algorithms, such as Ethash. PDLs and additional RAM helps us to solve problem of implementation of different hashing algorithms in one circuit from the hardware perspective.
  5. Switch between different algorithms is done via reboot of device. Users reboots ASIC and chooses certain algorithm, then PDL automatically changes algorithm of generating hashes (that is already stored on ROM as mentioned above). After that process of switching is complete and ASIC is ready for mining.

Pascal A1 ASIC architecture. Example of work with Ethash algorithm

1.        General understanding of Ethash mining algorithm

The general route that the algorithm takes is as follows:

  • There is a seed that can be computed for each block by scanning through the block headers up until that point.
  • From the seed, one can compute a 16 MB pseudorandom cache. Light clients store the cache.
  • From the cache, we can generate a 1 GB dataset, with the property where each item in the dataset depends on only a small number of items from the cache. Full clients and miners store the dataset. The dataset grows linearly with time.
  • Mining involves grabbing random slices of the dataset and hashing them together. Verification can be done with low memory by using the cache to regenerate the specific pieces of the dataset that you need, so you only need to store the cache.

The large dataset is updated once every 30000 blocks, so the vast majority of a miner's efforts will be reading the dataset, not making changes to it.

Ethash algorithm maintain a "mix" 128 bytes wide, and repeatedly sequentially fetch 128 bytes from the full dataset and use function to combine it with the mix. 128 bytes of sequential access are used so that each round of the algorithm always fetches a full page from RAM, minimizing translation lookaside buffer misses which ASICs are able to avoid.

2.        Consider the Pascal A1 architecture of the sample with the algorithm Ethash

Actually, mining of Ethash on CPU is not profitable, and there is no ASIC device for mining of Ether, because Directed acyclic graph (DAG) algorithm requires large memory size and needs at least 1-2GB RAM for each processor according to existing manual, but de facto nowadays user needs to have at least 8GB of RAM. Our ASIC will have 64GB of shared RAM + extra 32GB of RAM specifically for mining such types of coins as Ethereum.

Additionally, to overcome this limitation, we develop principally new architecture of our ASIC with two processors’ core in the form of programmable logic device (PLD) on Altera.

PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, that has a fixed function, a PLD has an undefined function at the time of manufacture. PLD must be properly programmed to be able to perform reconfiguration of a circuit.

Two PLD modules on the board allow us to work simultaneously with two mining algorithms with high capacity, while addition of ROM and extra RAM memory (32GB) allows ASIC to mine such demanding algorithms as Ethash.

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